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决议: 10 Bit 渠道: 1 Channel DNL: ±0.5 LSB INL: ±0.5 LSB 压摆率: 2 V/µs -
决议: 12 Bit 渠道: 1 Channel DNL: ±1 LSB INL: ±1 LSB 压摆率: 2 V/µs
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决议: 10 Bit 渠道: 1 Channel DNL: ±0.5 LSB INL: ±4 LSB 压摆率: 0.5 V/µs
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决议: 12 Bit 渠道: 1 Channel DNL: ±1 LSB INL: ±16 LSB 压摆率: 0.5 V/µs
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决议: 8 Bit 渠道: 4 Channels DNL: ±0.25 LSB INL: ±0.25 LSB 压摆率: 1 V/µs
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决议: 10 Bit 渠道: 4 Channels DNL: ±0.5 LSB INL: ±0.5 LSB 压摆率: 1 V/µs
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决议: 12 Bit 渠道: 4 Channels DNL: ±1 LSB INL: ±1 LSB 压摆率: 1 V/µs
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决议: 12 Bit 渠道: 4 Channels DNL: ±1 LSB INL: ±1 LSB 压摆率: 1 to 150 mA/Fs
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决议: 8 Bit 渠道: 2 Channels DNL: ±0.5 LSB INL: ±1 LSB 压摆率: 0.5 V/µs
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决议: 10 Bit 渠道: 2 Channels DNL: ±0.5 LSB INL: ±4 LSB 压摆率: 0.5 V/µs
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决议: 12 Bit 渠道: 2 Channels DNL: ±1 LSB INL: ±16 LSB 压摆率: 0.5 V/µs
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决议: 8 Bit 渠道: 8 Channels DNL: ±0.25 LSB INL: ±0.25 LSB 压摆率: 1 V/µs
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决议: 10 Bit 渠道: 8 Channels DNL: ±0.5 LSB INL: ±0.5 LSB 压摆率: 1 V/µs
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决议: 12 Bit 渠道: 8 Channels DNL: ±1 LSB INL: ±1 LSB 压摆率: 1 V/µs
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决议: 10 Bit 渠道: 4 Channels DNL: ±0.5 LSB INL: ±4 LSB 压摆率: 0.5 V/µs
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决议: 12 Bit 渠道: 4 Channels DNL: ±1 LSB INL: ±16 LSB 压摆率: 0.5 V/µs
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决议: 8 Bit 渠道: 1 Channel INL: ±1 LSB 沉淀时间: 5 µs 输出类型: Voltage - Buffered
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决议: 8 Bit 渠道: 4 Channels DNL: ±1 LSB INL: ±0.5 LSB 输出类型: Voltage - Buffered
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决议: 8 Bit 渠道: 4 Channels DNL: ±1 LSB INL: ±1 LSB 输出类型: Voltage - Buffered
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决议: 10 Bit 渠道: 1 Channel INL: ±9 LSB 沉淀时间: 0.5 µs 增益误差: 0.3% FSR